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order this document by AN1746/d AN1746 migrating from the mc68hc705k1 to the mc68hc705kj1 by mark glenewinkel field applications engineering consumer systems group austin, texas introduction freescale provides two different parts to migrate your current mc68hc705k1 (k1) application easily. depending on your design, system enhancements, and cost, the mc68hc705kj1 (kj1) and the mc68hc805k3 (k3) provide two different migration paths. the major differences between the kj1 and the k3 are: ? price ? pinout compatibility the kj1 is not pin for pin the same as the k1, but it is roughly 70% the cost of the k1. although the k3 is pin for pin the same as the k1, it is roughly 90% the cost of the k1. this application note illustrates the differences between the k1 and the kj1. using the kj1s additional features can further enhance your system design. consult the k1 and kj1 databooks for detailed design reference. see references/additional reading in this application note. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . freescale semiconductor ? freescale semiconductor, inc., 2004. all rights reserved.
application note AN1746 for information on migrating your design to the k3, consult the application note titled migrating from the mc68hc705k1 to the mc68hc805k3, freescale document order number an1747/d. mc68hc705kj1 features ? 1240 bytes of user eprom ? 64 bytes of low-power user ram ? 4-mhz maximum internal bus frequency at 5 volts ? 15-stage multifunction timer ? cop watchdog timer ? 10 bidirectional input/output (i/o) pins, including: C 10-ma sink capability on all i/o pins C 5.5-ma source capability on six i/o pins C software programmable pulldowns on all i/o pins C keyboard scan with selectable interrupt on four i/o pins ? selectable sensitivity on external interrupt; edge- and level- sensitive or edge-sensitive only ? on-chip oscillator with options for: C crystal C ceramic resonator C resistor-capacitor (rc) oscillator (mc68hrc705kj1) with or without external resistor C low-speed (32 khz) crystal (mc68hlc705kj1) C external clock ? external interrupt mask bit and acknowledge bit ? eprom security bit 1 to aid in locking out access to programmable eprom array ? selectable stop conversion to halt and option for fast restart and power-on reset ? internal steering diode and pullup device on reset pin to v dd 1. no security feature is absolutely secure. however, motorolas strategy is to make reading or copying the eprom/otprom difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 migrating to the mc68hc705kj1 pinouts and package types the kj1 has a different pinout from the k1, making layout changes necessary. see figure 1 and figure 2 for pin descriptions. both parts are available in either plastic dip or soic packages. figure 1. mc68hc705k1 pinout figure 2. mc68hc705kj1 pinout reset osc1 osc2 v ss v dd pa 7 pa 6 pa 5 pa 4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pb1/osc3 pb0 irq/v pp pa 0 pa 1 pa 2 pa 3 irq/v pp pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc1 osc2 pb3 pb2 v dd v ss pa 7 reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 block diagrams throughout this application note, refer to the block diagrams for the k1 in figure 3 and kj1 in figure 4 . figure 3. mc68hc705k1 block diagram data direction register b port b pb1/osc3 pb0 0 00 0000011 cpu control arithmetic/logic unit accumulator index register stack pointer 0 00 program counter 00 m68hc05 mcu reset condition code register 111hi ncz data direction register a port a pa7* pa6* pa5* pa4* pa3** pa2** pa1** pa0** *8-ma-sink capability **external interrupt capability cop watchdog and internal oscillator divide by two multifunction illegal address detect low-voltage irq/v pp v dd v ss osc1 osc2 personality eprom/otprom 64 bits user ram 32 bytes reset mask option register (eprom/otprom) user eprom/otprom 504 bytes 1 0 timer cpu clock timer clock detect f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 figure 4. mc68hc705kj1 block diagram 0000000011 watchdog and illegal address detect static ram (sram) C 64 bytes alu cpu control 68hc05 cpu accumulator index register stk ptr program counter condition code register 15-stage multifunction timer system divide internal oscillator osc1 osc2 cpu registers user eprom C 1240 bytes mask option register (eprom) 10-ma sink capability on all i/o pins data direction register a data direction register b port a port b pb3 (1) pb2 (1) pa7 pa6 pa5 pa4 pa3 (1) (2) pa2 (1) (2) pa1 (1) (2) pa0 (1) (2) reset irq/v pp 111hinzc by 2 notes: 1. 5.5-ma source capability 2. external interrupt capability f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 memory maps and registers figure 5 and figure 6 show the memory maps and registers of the k1 and kj1. modify your code to reflect these changes: ? the kj1 has a total of 64 bytes of ram. if you want to utilize this additional memory of the kj1, originate ram memory to start at $c0. ? the kj1 has a total of 1232 bytes of eprom for code space. originate eprom memory to start at $300. ? move the mor register from location $17 on the k1 to location $7f1 on the kj1. ? move the location of the cop register from location $3f0 on the k1 to location $7f0 on the kj1. ? move the start of the interrupt vectors from location $3f8 on the k1 to location $7f8 on the kj1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 figure 5. mc68hc705k1 memory and register map port a data register timer interrupt vector (msb) timer interrupt vector (lsb) external interrupt vector (msb) external iinterrupt vector (lsb) software interrupt vector (msb) software interrupt vector (lsb) reset vector (msb) reset vector (lsb) $000f $000e $0009 $0008 $0007 $0006 $0005 $0004 $0003 $0002 $0001 $0000 $03f8 $03f9 $03fa $03fb $03fc $03fd $03fe $03ff port b data register port a data direction register port b data direction register ? ? ? cop register $03f0 unused 192 bytes $0000 $001f $03ff i/o registers 32 bytes user vectors eprom 8 bytes test rom and 8 bytes $03f7 $01ff unused 256 bytes sram 32 bytes unused unused unused unused timer counter register timer status and control register $000a irq status and control register $0200 $00df $00e0 $0020 $00ff $0100 $03f8 user eprom 496 bytes reserved 7 bytes $03ef $03f0 32 bytes $0010 $0011 $0012 stack cop register unused unused unused peprom bit select register $000c $000b $000d peprom status and control register pulldown register a pulldown register b $001f $001e $0019 $0018 $0017 $0016 $0015 $0014 $0013 $001a $001c $001b $001d unused unused unused unused unused mask option register eprom programming register unused unused unused unused unused unused test sram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 figure 6. mc68hc705kj1 memory and register map port a data register timer interrupt vector (msb) timer interrupt vector (lsb) external interrupt vector (msb) external iinterrupt vector (lsb) software interrupt vector (msb) software interrupt vector (lsb) reset vector (msb) reset vector (lsb) $000f $000e $0009 $0008 $0007 $0006 $0005 $0004 $0003 $0002 $0001 $0000 $07f8 $07f9 $07fa $07fb $07fc $07fd $07fe $07ff port b data register port a data direction register port b data direction register ? ? ? cop register $07f0 unused 160 bytes $0000 $001f $07ff i/o registers 32 bytes registers & vectors (eprom) 16 bytes test rom 2 bytes $07ef $02ff unused 512 bytes sram 64 bytes unused unused unused unused timer counter register timer status and control register $000a irq status and control register $0300 $00bf $00c0 $0020 $00ff $0100 $07f0 user eprom 1232 bytes reserved 6 bytes $07ed $07ee 64 bytes $0010 $0011 $0012 unused unused unused $000c $000b $000d pulldown register a pulldown register b $001f $001e $0019 $0018 $0017 $0016 $0015 $0014 $0013 $001a $001c $001b $001d unused unused unused unused unused eprom programming register unused unused unused unused unused unused reserved unused unused unused mask option register $07f1 $07cf $07d0 unused 30 bytes stack sram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 ports the kj1 i/o pins have expanded high current capabilities that allow them to source or sink current to a device. depending on the current requirements, these pins can be used to switch power to other parts of the system, light leds, or switch opto-coupled triacs without external transistors. table 1 shows the maximum ratings for the i/o pins. consult the kj1 databook for high-side and low-side driver characteristics and graphs. port a no changes needed on port a. port b the kj1 has two bits of the port b register bonded out. these are bits 2 and 3. change your code by mapping the k1s port b pins to the kj1s port b pins. this mapping also applies to the port b data direction register and the port b pulldown register. k1 pb0 maps to kj1 pb2. k1 pb1 maps to kj1 pb3. table 1. kj1 i/o maximum current ratings characteristic symbol max unit high source current pa7Cpa4 pins pa3Cpa0 pins pb3Cpb2 pins i oh 2.5 5.5 5.5 ma high sink current pa7Cpa0 pins pb3Cpb2 pins i ol 10 10 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 figure 7. port b data register (portb) figure 8. port b data direction register (ddrb) figure 9. pulldown register b (pdrb) $0001 bit 7 654321 bit 0 read: 0 0 see note see note pb3 pb2 see note see note write: reset: unaffected by reset = unimplemented pb5, pb4, pb1, and pb0 should be configured as inputs at all times. these bits are avail- able for read/write but are not available externally. configuring them as inputs will en- sure that the pulldown devices are enabled, thus properly terminating them. $0005 bit 7 654321 bit 0 read: 0 0 see note see note ddrb3 ddrb2 see note see note write: reset: 00000000 = unimplemented pb5, pb4, pb1, and pb0 should be configured as inputs at all times. these bits are avail- able for read/write but are not available externally. configuring them as inputs will en- sure that the pulldown devices are enabled, thus properly terminating them. $0011 bit 7 654321 bit 0 read: 0 0 see note see note pdib3 pdib2 see note see note write: reset: 00000000 = unimplemented pb5, pb4, pb1, and pb0 should be configured as inputs at all times. these bits are avail- able for read/write but are not available externally. configuring them as inputs will en- sure that the pulldown devices are enabled, thus properly terminating them. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 clock the kj1 has different clock circuitry than the k1. the main difference is the rc clock option. the available clocking options on the kj1 are listed in table 2 . if you are using a crystal or ceramic resonator and want to use the internal feedback resistor, the oscres bit in the mask option register (mor) must be set to 1. this enables the 2-m w feedback resistor. the kj1 has the option of using a 32-khz crystal. consult the kj1 databook about how to connect a 32-khz crystal to the kj1 properly. the rc option on the kj1 is quite different from the k1. the rc oscillator has two options: ? for more accurate clocks, use an external resistor between the osc1 and osc2 pins. do not turn on the internal feedback resistor. make sure the oscres bit in the mor is 0. ? for maximum cost reduction, the rc oscillator can utilize the internal resistor and allow the chip to be driven with no external components. this is also the least accurate way to clock the chip. to use this option, make sure that the oscres bit in the mor is 1. like the k1, the kj1 can be driven by an external clocking source also. table 2. kj1 clock options clock option comments part number crystal oscillator internal feedback resistor con gured in mor mc68hc705kj1 crystal oscillator (32 khz) do not use internal feedback resistor mc68hlc705kj1 ceramic resonator internal feedback resistor con gured in mor mc68hc705kj1 rc oscillator uses either external or internal resistor mc68hrc705kj1 external clock direct connection of clock source mc68hc705kj1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 for applications that demand more performance, the kj1 maximum internal clock frequency is 4 mhz. the k1 maximum internal clock frequency is 2 mhz. reset and lvr circuitry the reset function on the kj1 has additional features: ? the reset pin contains a steering diode to discharge any voltage on the pin to v dd when the power is removed. ? the reset pin contains an internal pullup resistor to v dd to allow the reset pin to be left unconnected for low-power applications. ? the kj1 has all of the k1 reset sources except a low-voltage reset (lvr). these are: C power-on reset C logic 0 on the reset pin C computer operating properly (cop) C illegal address the kj1 does not have an internal lvr. if your k1 design used the lvr, external lvr circuitry must be added to replace this function. interrupts like the k1, the kj1 has the same interrupt sources and functionality. these are: ? software interrupt ? logic 0 applied to the irq/v pp pin ? logic 1 applied to one of the pa3Cpa0 pins ? a timer overflow interrupt ? a real-time interrupt the port a interrupt option on the k1 is programmed by writing to the pirq bit (bit 2) of the mor at location $17. on the kj1, write to the pirq bit (bit 2) of the mor at location $7f1. the external interrupt sensitivity on the k1 is programmed by writing to the level bit (bit 1) of the mor at location $17. on the kj1, write to the level bit (bit 1) of the mor at location $7f1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note migrating to the mc68hc705kj1 AN1746 timer the timer on the kj1 is identical to the k1. no changes are needed in software or hardware. cop the cop on the k1 is enabled by programming the copen bit (bit 0) of the mor at location $17 to a 1. on the kj1, program the copen bit (bit 0) of the mor at location $7f1 to a 1. the k1 cop timer is cleared by writing a 0 to bit 0 of the copr (computer operating properly register) at location $3f0. on the kj1, clear the cop by writing a 0 to bit 0 of the copr located at $7f0. just like the k1, the kj1 cop timeout is set by the rt1 and rt0 bits of the timer status and control register. no code changes are needed. personality eprom the k1 provides the user with 64 bits of personality eprom. the kj1 does not have a personality eprom array. consequently, the personality eprom bit select register and the personality eprom status and control register are not found on the kj1. to provide this functionality within the kj1, utilize some of the extra eprom on the kj1 to create eight bytes or 64 bits of personality eprom. this eprom memory cannot be programmed by the users code. it can be programmed only at the time the entire eprom array is being programmed for production. mor the kj1 gives the designer additional options in the mor. table 3 compares the two mor registers. table 3. mor comparison part bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 k1 swpdi pin3 rc swait lvre pirq level copen kj1 soscd epmsec oscres swait swpdi pirq level copen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note AN1746 swpdi the software pulldown inhibit bit has the same functionality on both parts but is found at bit 3 of the kj1 mor. pin3 since the kj1 does not have a 3-pin oscillator option, this option is not found on the kj1 mor. rc the rc option on the k1 was used to distinguish between using an external rc network or an external crystal, ceramic resonator, or clock source. the kj1 configures its oscillator with the oscres bit. swait the stop conversion to wait bit has the same functionality on both parts. lvre the kj1 does not have a low-voltage reset function. this option is not found in the kj1 mor. pirq the port a irq enable bit has the same functionality on both parts. level the external interrupt sensitivity bit has the same functionality on both parts. copen the cop enable bit has the same functionality on both parts. soscd the short oscillator delay bit controls the oscillator stabilization counter. the normal stabilization delay following reset or exit from stop mode is 4064 bus cycles. setting the soscd enables a 128-bus cycle stabilization delay. if your oscillator design has a quick startup time, the soscd bit will allow quicker recovery from oscillator startup. setting the bit to a 1 enables the short oscillator delay. epmsec to protect your software investment, the kj1 provides the designer the added functionality of securing the eprom array. when this bit is set, external access of the eprom array is denied. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
application note ordering information AN1746 oscres the oscres bit enables the 2-m w internal resistor in the oscillator circuit. when this bit is set to 1, the internal resistor is enabled. note: program the oscres bit to logic 0 in devices using low-speed crystal oscillators or rc oscillators with external resistors. ordering information table 4 lists the mc order numbers for the kj1. all parts are specified to run at C40 to +85 c temperature. table 4. ordering information package type oscillator type order number plastic dip xtal mc68hc705kj1cp soic xtal mc68hc705kj1cdw cerdip xtal mc68hc705kj1cs plastic dip rc mc68hrc705kj1cp soic rc mc68hrc705kj1cdw cerdip rc mc68hrc705kj1cs plastic dip 32-khz xtal mc68hlc705kj1cp soic 32-khz xtal mc68hlc705kj1cdw cerdip 32-khz xtal mc68hlc705kj1cs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required application note references/additional reading mc68hc705k1 technical data , (mc68hc705k1/d),. mc68hc705kj1 technical data, (mc68hc705kj1/d), f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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